1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device, and more particularly, to a manufacturing method of those devices which use STI (shallow trench isolation) for isolation of elements.
2. Description of the Related Art
Recently, isolation of elements by SA-STI (self-aligned shallow trench isolation) has come be employed in place of conventional LOCOS methods as a method for isolation of elements required for miniaturization of semiconductor devices. One of problems with isolation of elements using STI is the nonvolatile semiconductor storage device which needs to generate a high potential for effecting erase/program(write) operations using a tunnel oxide film.
The nonvolatile semiconductor storage device needs, in addition to a memory cell transistor requiring a tunnel oxide film, a transistor with a thick gate oxide film for generating a high potential (high voltage-withstanding transistor) and a thin gate oxide film for effecting low-power, low-voltage operations (low voltage-withstanding transistor). That is, it needs three kinds of transistors: memory cell transistor, high voltage-withstanding transistor, low voltage-withstanding transistor. For making these three kinds of transistors, thickness of the oxide film of the low voltage-withstanding transistor is the thinnest, thickness of the tunnel oxide film of the memory cell transistor is the next, and thickness of the oxide film of the high voltage-withstanding transistor is the thickest. On the other hand, thickness of the tunnel oxide film of the memory cell transistor may be the thinnest, thickness of the oxide film of the low voltage-withstanding transistor may be the next, and thickness of the oxide film of the high voltage-withstanding transistor may be the thickest.
In these nonvolatile semiconductor storage devices requiring differentiation in thickness among a plurality of gate oxide films, deterioration of the transistor performance by depression of STI arises as a problem. FIG. 12 is a cross-sectional view of a nonvolatile semiconductor storage device under its manufacturing process, taken to explain depression of STI, and FIG. 13 is a plane view taken from the top of FIG. 12. That is, FIG. 12 is a cross-sectional view taken along the A--A line of FIG. 13. These FIGS. 12 and 13 illustrate a MOS transistor.
As shown in FIGS. 12 and 13, depressions 106 appear in STI regions 104. The depressions 106 in the STI regions 104 are caused by a film decrease in the STI regions 104 upon oxide film etching conducted for forming an oxide film different in thickness from the gate oxide film 108 in the active regions 102 of the semiconductor substrate 100. When the film decrease occurs, surfaces of the STI regions 104 in the perimeter portions sink into the semiconductor substrate 100 from the surface level of the active region 102.
As shown in FIG. 13, once the depressions 106 are produced at perimeter portions of the STI regions 104 to surround the active regions 102, as shown in FIG. 12, gate electrodes 110 also sink into the depressions 106. When the gate electrodes 110 sink, the depressed perimeter regions are affected by side surface portions of the active regions 102, and invite the anomaly that kinks occur in sub-threshold regions of MOS transistors. FIG. 14 is a diagram which shows relationship between the gate voltage Vg and log Id of the source/drain current Id of a transistor including kinks.
As shown in FIG. 14, when kinks occur, the cut-off property of the MOS transistor deteriorates, and the off leakage current increases. This invites various problems such as instability of the circuit operation, increase of power consumption in the standby mode.